Task 1
1) Compose two test vectors for a given short
defect in a given circuit: one for wiredAND
fault model and one for WiredOR.
2) Apply an exhaustive test to the corresponding
defective circuit and obtain the truth table.
Fill in the Karnaugh map.
3) Find all test vectors for the given defect.
Use Karnaugh maps of the original function and
the defective one.
4) Using the previous results, check which one
of your vectors detects the defect.
5) Which fault model WiredAND or WiredOR does
better describe the defect behavior model?
Task 2
1) Manually find all possible test vectors for
a given short between circuit’s input and
output using VictimAggressor fault model. Consider
both cases:
a) when output is aggressor and input is victim
b) when input is aggressor and output is victim
2) Apply an exhaustive test to the corresponding
defective circuit and obtain the defect table.
3) Compare your test vectors with the corresponding
column from the defect table.
4) Make conclusion about real victim and aggressor.
Task 3
1) Generate minimallength stuckat fault
(SAF) test for a given circuit.
2) Apply this test to all SAFs of the circuit
and check if they are covered. If not, correct
the test and apply again.
3) Apply the same test to all defects in given
circuit and check if they are covered.
4) For undetected defects, find appropriate
test patterns using transistorlevel schematic.
5) Check using DefSim, if your final test set
is complete.
Task 4
1) Obtain the defect table for a given circuit.
2) Apply the exhaustive test to a given unknown
defect and obtain detecting information.
3) Analyze the data in order to localize the
unknown defect.
Task 5
1) Identify all shorts in c17 that are capable
to convert this combinational circuit into a
sequential one.
2) Find test vectors for one of such shorts.
